1. Field of the Invention
This invention relates to an integrated logic circuit employing normally-off type field effect transistors such as metal Schottky-barrier-gate FET's (Si MESFET's and compound MESFET's) and junction gate FET's (JFET's).
An integrated logic circuit employing GaAs FET's is receiving a great deal of attention as a high-speed data processing IC. Basic logic gate circuits employing GaAs FET's include those which use normally-on type GaAs FET's and those which use normally-off type GaAs FET's. Although circuits of the latter category involve difficult manufacturing procedures, they can be realized by the simplest configuration. The latter logic circuits are therefore expected to realize an highly integrated logic circuit employing GaAs FET's.
Meanwhile most basic logic gates of an integrated logic circuit are NOR gates and NAND gates. A complex logic function is realized with a silicon logic IC by arbitrarily combining these NOR and NAND gates. On the other hand, an integrated logic circuit employing normally-on type GaAs FET's consists of NOR gates but rarely of NAND gates. This does not imply that NAND gates are unnecessary, but the configuration of the NAND gates causes some difficulty, details of which will be described hereinafter
2. Description of the Prior Art
An integrated logic circuit employing GaAs FET's generally comprises metal Schottky-barrier-gate FET's or Schottky-gate FET's (to be referred to as MESFET's hereinafter), or junction gate FET's (to be referred to as JFET's hereinafter). In an integrated logic circuit employing normally-off type GaAs FET's, these FET's are used with a positive bias voltage with respect to the source potential, applied to their gates, so that a forward current flows from their gates to the channels. FIGS. 1(A) and 1(B) show examples of an inverter and a NOR gate each using a normally-off type GaAs FET or FET's. In these circuits, when the logic level of an input is HIGH ("1"), a forward current may flow from the gate to a grounded source electrode. Accordingly the gate potential is clamped to the voltage determined by the rise voltage of this forward current (about 0.7 V in the case of a MESFET and about 1.2 V in the case of a JFET). If a NAND gate constructed by normally-off type MESFET's, Si MESFET's or JFET's, the following problem is encountered. FIG. 2 shows a NAND gate consisting of normally-off type FET's Q1 and Q2 and a resistor R1; and an inverter consisting of an FET Q3 and a resistor R2, this inverter being connected to receive an output from the NAND gate. In the NAND gate shown in FIG. 2, when the input logic level of the gate input terminal IN2 of the FET Q1 is LOW ("0") to turn it off, and when the logic level of the gate input terminal IN1 of the FET Q2 at the side of a power supply VDD is HIGH ("1") to turn it on, a forward current I1 of the gate input terminal IN1 is not allowed to flow into the source of the FET Q1 since it turns OFF. However, in the actual circuit, since the output of the NAND gate is connected to the gate input terminal of the inverter as the next stage, the forward current I1 practically flows to the FET Q3 through a drain electrode D2 of the FET Q2. At this time, current I1, I2 and I3 may flow to the FET Q3, as illustrated in the figure.
In general the MESFET comprises, as shown in FIG. 3, a gate electrode 16 for defining a Schottky contact 14 with the surface of an active layer 12 formed on a substrate 10, and a source electrode 18 and a drain electrode 20 for defining ohmic contact with the layer 12. Since the active layer 12 is very thin, a considerably large series resistance Rs is present, as schematically shown in FIG. 3. Therefore, in the state of the circuit shown in FIG. 2, the effective source potential of the FET Q3 is given by Rs.multidot.(I1+I2+I3).
The potential of the source S3 of the FET Q3 (inverter) receiving signals from the output terminal of the NAND gate is further increased by the voltage defined by Rs.multidot.I1, compared with in the case of sole NOR gate or inverter, rendering the holding of the "0"level difficult. For this reason, a NAND gate employing normally-off type GaAs FET's has not been used in an integrated logic circuit.